Device for simulating the locating signals of an ILS beacon

ABSTRACT

The present invention relates to a device for simulating the locating signals of an I L S beacon, said device comprising on the one hand two chains in parallel respectively intended for generating sinusoidal modulation I L S signals, each comprising a digital generator for one of said signals and a digital analog converter provided with an input for controlling the reference amplitude of its output voltage and, on the other hand, an at least partially digital arrangement for producing reference voltages for said inputs for controlling the digital/analog converters. The invention is applicable for testing apparatus on board an aircraft.

The present invention relates to a device for simulating locating signals emitted by an I L S beacon of known type (Instrument Landing System). Such a device is intended to test the apparatus on board an aircraft for example, adapted to receive and exploit the signals emitted by an I L S beacon to determine the position of said aircraft with respect to said beacon.

It is known that, with a view to determining the position of an aircraft with respect to the longitudinal axis of an aerodrome runway, an I L S beacon comprises an antenna system, of which the radiation pattern comprises two elongated lobes, symmetrical with respect to said runway axis, one of the lobes corresponding to a high frequency signal carrying a sinusoidal modulation signal at 90 Hz, the other lobe corresponding to a high frequency signal carrying a sinusoidal modulation signal at 150 Hz. The emission powers of the two lobes are equal. Thus, according to whether the aircraft is located to the left or to the right of the axis of the runway, the amplitude of one of the modulation signals received by the aircraft is greater than that of the other of said signals, and vice versa. When the aircraft is just in the axis of the runway, the amplitudes of these modulation signals are equal. It is therefore easily understood that such a beacon is particularly useful when an aircraft is landing.

It is therefore particularly important that the apparatus on board the aircraft are tested and adjusted with a strict precision, particularly in amplitude.

It is an object of the present invention to provide a device for simulating I L S locating signals allowing such a test and such an adjustment, as it offers, due to its structure, a strict precision of amplitude.

To this end, according to the invention, the device for simulating the locating signals of an I L S beacon, comprising an antenna system, of which the radiation pattern comprises two elongated lobes, symmetrical with respect to a longitudinal axis, each of said lobes corresponding to a high frequency signal carrying a low frequency sinusoidal modulation signal, said low frequencies being different from each other and specific of the lobe to which they correspond, is noteworthy in that it comprises on the one hand, two chains in parallel, respectively intended for the generation of said sinusoidal modulation signals and each comprising a digital generator for producing one of said signals and a digital/analog converter provided with an input for controlling the reference amplitude of its output voltage and, on the other hand, an at least partially digital arrangement to produce reference voltages for said inputs for controlling the digital/analog converters.

Thus, due to such a structure, for a large part digital, it is possible to control, with precision, the amplitude of said sinusoidal modulation signals.

These generators, when they are intended to produce a sinusoidal signal of frequency f, by means of the synthesis of N dots per period, each comprise a first forward-backward counter receiving from a clock a signal of frequency at least approximately equal to N.f and transmitting its state to a memory in which to each of these states there corresponds a logic level 1 or 0 according to whether or not it is necessary to increment the preceding totalised value to follow the most faithfully the function to be synthesized, a second forward-backward counter totalizer receiving this logic level 1 or 0 and a logic controlling said first and second forward-backward counter for forward counting or backward counting. The first forward-backward counter alternately counts the first N/4 clock pulses, and counts down the following N/4 clock pulses, whilst, in a cycle of N clock pulses, the second forward-backward counter counts during the first N/4 clock pulses, counts down during the following 2.N/4 clock pulses, and counts again during the N/4 clock pulses following these 2.N/4 pulses. The increment by which the preceding totalised value must or must not be increased may be constituted by said logic level 1 or 0.

The arrangement intended to produce the reference voltages for the digital/numerical converters advantageously comprises a resistor network connected to a supply voltage and comprising n resistors in parallel through which currents of intensity i₀, i₀ /2, i₀ /4 . . . i₀ /2^(n) respectively pass, said resistors each being able to be connected by bistable switches controlled at one or the other of a first or of a second output terminal, possibly by means of current/voltage converters, said second output terminal moreover receiving an additional current i₀ /2^(n).

Thus, by maintaining the switch which is connected to the resistor through which passes the current of intensity io, in its position of connection to the first terminal and by connecting the other switches either to the first terminal, or to the second terminal, it is possible to obtain thereon voltages respectively equal to V+ΔV and V-ΔV, the variation ΔV being adjustable by tipping certain of said other switches.

The outputs of the digital/analog converters of the two chains are connected to an adder.

It is advantageous if the two chains are controlled in parallel by a common pilot oscillator of which the frequency is equal to the product of the lowest common multiple of the low frequencies f₁ and f₂ of the two sinusoidal modulation signals and of the number N of the dots of synthesis per period of said signals.

In this case, it is indispensable to provide in each chain, upstream of the digital generator, a digital divider adapted to supply said generator with the frequency N.f₁ or N.f₂ which corresponds thereto.

However, as the above-described arrangement furnishes voltages V+ΔV and V-ΔV, to be able to simulate both the case where the amplitude of the modulation signal of highest frequency is greater than the amplitude of the modulation signal of lowest frequency and the case of the amplitude of lowest frequency being greater than the amplitude of the signal of highest frequency, it is indispensable that each digital divider comprises two ratios of division so that each of the chains can produce one or the other of said low frequencies f₁ or f₂, so that, when one of the chains produces the modulation signal of frequency f₁, the other chain simultaneously produces the modulation signal of frequency f₂, and vice versa.

In order tp be able to simulate a "phase shift" between the two sinusoidal modulation signals, the device according to the invention comprises a digital phase converter with control inputs, disposed between the two chains and capable, from the passage through the 0 degree phase of the sinusoidal modulation signal produced by one of the digital generators, to initialize the other sinusoidal modulation signal with a variable delay. Such a phase converter is advantageously constituted by a digital counter with programmable counting value.

Such a counter, on the one hand, counts the pulses which arrive from a third divider connected to one of said digital generators and presenting, as desired, two ratios of division equal to those of said chain dividers and, on the other hand, is controlled by a fourth divider connected to one of said chain dividers, the radios of division of said third and fourth dividers being simultaneously equal to each other and inverse of the ratio of division of the divider of the chain from which they receive their data.

The invention will be more readily understood on reading the following description with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating the structure of an I L S simulating device according to the invention.

FIG. 2 is the diagram of a digital/analog converter for varying the amplitude of the modulation signals.

Referring now to the drawings, the I L S simulator shown in FIG. 1 allows the generation of two sinusoidal signals, at 90 and 150 Hz respectively, the relative amplitudes of which may be adjusted very precisely, since this simulator essentially comprises a digital structure. Moreover, this simulator makes it possible to adjust the phase of these two sinusoidal signals with respect to their common subharmonic at 30 Hz. The gist of the present invention is to produce in digital manner the two sinusoidal signals, this enabling the level of said signals to be very precisely controlled with the aid of a D.C. voltage applied to the reference input of the digital/analog converters, provided downstream of said digital generators.

To this end, the simulator of FIG. 1 comprises, between a high frequency pilot oscillator 1 and an operational amplifier 2 mounted as adder, two generation chains mounted in parallel, said oscillator 1 and said adder 2 being common to the two chains.

Each chain comprises a programmable divider 3 or 4 receiving the pulses from the pilot generator 1, a digital generator of sinusoidal signal 5 or 6 controlled by said divider 3 or 4, and a digital/analog converter 7 or 8 receiving the signals from the generator 5 or 6 and transmitting its own analog signals to the adder 2, at the output 9 of which appears a signal simulating that of an I L S beacon. Between the two chains 3,5,7 and 4,6,8 is disposed an amplitude control device 10, the inputs 11 and 12 of which receive reference signals and the outputs 13 and 14 of which control the reference inputs of the converters 7 and 8.

The pilot oscillator 1 produces a signal of frequency equal to 3600 to 450 Hz, in the case of a synthesis by 10th of degree being desired for the generation of the sinusoidal signals, this frequency being 3600 times the smallest common multiple of 90 and 150 Hz. The signal of the oscillator is transmitted to the dividers 3 and 4. These programmable dividers are identical and may each divide the frequency of the oscillator 1 by 3 and by 5 according to the orders sent onto their control inputs 15 and 16. Only the control (not shown) of the programmable dividers 3 and 4 is wired so that when the divider 3 divides by 3 the divider 4 divides by 5, whilst, when the divider 3 divides by 5, the divider 4 divides by 3. Thus, the generators 5 and 6 receive signals whose frequency is either 3600×90 or 3600×150, so that, when one receives the first frequency, the other receives the second, and vice versa.

This results in the generator 5 generating a digital sinusoidal signal at 150 Hz when the generator 6 generates a digital sinusoidal signal at 90 Hz and vice versa. These digital sinusoidal signals are converted into analog signals by the converters 7 and 8, respectively, and their sum appear at the output 9.

The device 10 is intended to vary the amplitude of the modulation signals at 90 or 150 Hz about a situation for which the amplitudes are equal, in order to simulate an aircraft position out of true with respect to the axis of the aerodrome runway.

FIG. 2 shows an embodiment for the device 10 for controlling the amplitude of the signals at 90 and 150 Hz, capable of producing at its outputs 13 and 14 control voltages V+ΔV and V-ΔV, applied on the reference inputs of the digital/analog converters 7 and 8

To this end, the device 10 comprises a multiple network of resistors comprising n resistors R₀ to R_(n-1) mounted in parallel and n resistors r₀ to r_(n-1) connecting the resistors R₀ to R_(n-1) together in twos at one of their ends, the resistor r₀ connecting the whole of the network to the terminal 11. At their end opposite the resistors R₀ to R_(n-1), the resistors R₀ to R_(n-1) are connected to bistable switches C₀ to C_(n-1). One of the positions of all the switches C₀ to C_(n-1) is connected to an input 17 of an operational amplifier 18 functioning as current/voltage converter; the other position of all the switches C₀ to C_(n-1) is connected to an input 19 of an operational amplifier 20, also functioning as a current/voltage converter. The outputs of the operational amplifiers 18 and 20 constitute the outputs 13 and 14 of the device 10, whilst the input 19 of the operational amplifier 20 is connected to the input terminal 12.

The network of resistors R₀ -R_(n-1) and r₀ -r_(n-1) is such that, when an adequate reference voltage is sent onto the terminal 11, the resistor R₀ has a current i₀ passing therethrough, the resistor R₁ a current i₀ /2, the resistor R₂ a current i₀ /4, etc. . . , the resistor R_(n-1) a current i₀ /2^(n). Moreover, there is applied on the terminal 12 an additional reference signal producing a current of intensity i₀ /2^(n), directed towards the input 19.

Thus, when the different switches C₀ to C_(n-1) occupy the positions shown in FIG. 2, i.e. the switch C₀ connects the resistor R₀ to the input 17 of the operational amplifier 18, whilst all the other switches C₁ to C_(n-1) connect the resistors R₁ to R_(n-1) to the input 19 of the operational amplifier 20), the operational amplifier 18 receives an input current i₁ equal to i₀, whilst the operational amplifier 20 receives an input current i₂, such that ##EQU1## in which the sum A comes from the part of network R₁ to R_(n-1) and the term B from the reference terminal 12.

It will easily be verified that the sum A+B is equal to i₀, i.e. i₂ =i₀.

Therefore, for the positions of switches C₀ to C_(n-1) shown in FIG. 2, i₁ =i₂ =i₀. This results in the control voltages which appear at the outputs 13 and 14 being equal to one another and to a common value V.

On the other hand, if, from the positions of switches shown in FIG. 2, one or more switches C₁ to C_(n-1) are made to tip, the switch C₀ remaining constantly in the position shown, it is easily imagined that the input current i₁ of the operational amplifier 18 becomes i₁ =i₀ +Δi, whilst the input current i₂ of the operational amplifier 20 becomes i₂ =i₀ -Δi. The voltages at the output terminals 13 and 14 have therefore respectively become equal to V+ΔV and V-ΔV. Of course, the amplitude of Δi, and therefore that of ΔV, depends on the number and row of two or that of the switches C₁ to C_(n-1) which have tipped with respect to the positions of FIG. 2.

Thus, the two control voltages elaborated by the device 10 appearing respectively at the terminals 13 and 14 thereof are such that their sum is constant (equal to 2V) and their difference (2ΔV) is directly proportional to the digital value furnished by the network R₀ -R_(n-1) and r₀ -r_(n-1), the value ΔV always being zero or positive.

The digital/analog converter 7 which receives from the digital generator 5 a sinusoidal signal, for example of the type Cos ω₁ t, with ω₁ =2πf₁, f₁ being equal to 150 or 90 Hz, therefore supplies at its output a signal of type (V+ΔV) Cos ω₁ t.

Similarly, the digital/analog converter 8, which receives from the digital generator 6 a sinusoidal signal, for example of the type Cos ω₂ t, with ω₂ =2πf₂, f₂ being equal to 90 or 150 Hz, therefore supplies at its output a signal of the type (V-ΔV) Cos ω₂ t.

At the output 9, an I L S simulation signal is therefore collected, of the type (V+ΔV) Cos ω₁ t+(V-ΔV) Cos ω₂ t.

Of the two voltages V+ΔV and V-ΔV, the first will always be equal to or greater than the second; consequently, the sinusoidal signal appearing at the output of the converter 7 will always be of amplitude equal to or greater than the sinusoidal signal appearing at the output of the converter 8. Thus, if the chain 3,5,7 were rigidly associated with the generation of a signal at 150 Hz and the chain 4,6,8 were rigidly associated with the generation of a signal at 90 Hz, the signal at 150 Hz would always have an amplitude greater than the signal at 90 Hz.

It is in order to be able to simulate the inverse case where the signal at 90 Hz has an amplitude greater than the signal at 150 Hz, that the dividers 3 and 4 are each provided to have two ratios of division, namely 3 and 5. Thus, the chain 3,5,7 may produce the signal at 90 (or 150) Hz of higher or equal amplitude, whilst the chain 4,6,8 may simultaneously produce the signal at 150 Hz (or 90 Hz) of lower or equal amplitude, according to the choice of the ratios of division of the dividers 3 or 4. By simple inversion of these ratios of division, it is therefore possible to obtain either the case of the amplitude of the signal at 90 Hz being greater than or equal to that of the signal at 150 Hz, or the inverse case.

The simulated position of an aircraft is translated not only by a difference in amplitude between the signals at 90 Hz and at 150 Hz, but also by a phase shift θ of one of the signals with respect to the other. To this end, the phase control in the simulator according to the invention is effected by a digital phase converter 21, constituted by a counter with programmed counting value, at the input 22 of which it is possible to introduce phase shifts θ, so that the signal actually appearing at the output of the converter 8 is of the type (V-ΔV) cos (ω₂ t+θ) and not only of the type (V-ΔV) cos ω₂ t, as mentioned previously. The simulated I L S signal at the output 9 therefore presents the form

    (V+ΔV) cos ω.sub.1 t+(V-ΔV) cos (ω.sub.2 t+θ)

The digital phase converter 21 produces a delay θ between the pulse of passage to the 0 degree phase of the sinusoidal signal of major amplitude (the one produced by the chain 3,5,7) and the pulse of initiation to the 0 degree phase of the sinusoidal signal of minor amplitude (the one produced by the chain 4,6,8). However, for the phase shift value θ to be independent of the ratio of division (3 or 5) of the divider 3, it is necessary to take into account, for the phase shift, only a single pulse every thirtieth of second (30 being the highest common factor of 150 and 90). Consequently, a divider 23 is provided, of which the ratio of division is 3 or 5 according to the value of the ratio of division of the divider 3 each time the product of said ratios of division being equal to 15, i.e. when the ratio of division of the divider 3 is equal to 3, that of the divider 23 is equal to 5, and vice versa. The choice of the ratio of division of the divider 23 is made by means of the control terminal 24. Moreover, the phase converter 21 must be synchronised by a clock whose frequency must be 3600×30 Hz so that the phase may be controlled by tenth of degree with respect to the common subharmonic at 30 Hz. This is effected by means of a divider 25 with two ratios of division 3 or 5 which may be chosen from a control terminal 26. When the ratio of division of the divider 3 is equal to 3, that of the divider 25 is equal to 5 and vice versa.

Thus, the device controlling the phase shift comprises on the one hand the phase converter 21 controlling the generator 6 and itself controlled by the divider 23 which receives from the generator 5 a pulse of passage through 0 of the sinusoidal signal produced by this latter, and, on the other hand, the divider 25 receiving the output signal from the divider 3 and synchronising the functioning of the phase converter 21.

It will be noted that the switching between the frequencies 90 Hz and 150 Hz at the level of the generation makes it possible to maintain in the device 10 the heavy weight (resistor R₀ -switch C₀) of the digital signal elaboring the two control voltages V+ΔV and V-ΔV applied on the input 17 of the operational amplifier 18. Thus, by construction, a strict equality may be obtained between the differences in modulation for the amplitude of signal at 90 Hz greater or lower than that of the signal at 150 Hz. Moreover, near the zero value of ΔV, where considerable precision is demanded of an I L S simulator, only the low weights (resistors R₁ to R_(n-1) switch C₁ to C_(n-1)) are used. For this use, a digital.analog converter 10 may thus be used, of which the precision is much less than its resolution and which is consequently inexpensive.

Moreover, it will be noted that with the device according to the invention, the sum of the amplitudes of the two sinusoidal signals remains constant whatever the value of amplitude difference chosen and may be rendered variable by acting on the reference signals applied on the control terminals 11 and 12 of the device 10. 

What I claim is:
 1. A device for simulating the locating signals emitted by an ILS beacon having a radiation pattern comprising two elongated lobes, each of which lobes is symmetrical with respect to a longitudinal axis and corresponds to a high frequency signal carrying a low frequency sinusoidal modulation signal, said low frequencies being different from each other and each being specific to the lobe to which it corresponds,said device comprising two chains in parallel respectively adapted for the generation of said sinusoidal modulation signals, wherein each chain comprises a digital generator for one of said signals and a digital/analog converter provided with an input for controlling the reference amplitude of its output voltage and wherein said device comprises an at least partially digital arrangement for producing reference voltages applied to said inputs for controlling said digital/analog converters.
 2. A device according to claim 1, in which the arrangement for producing said reference voltages comprises a resistor network connected to a supply voltage and comprising n resistors in parallel through which currents of intensity i₀, i₀ /2, i₀ /4 . . . i₀ /2^(n) respectively pass, wherein each said resistor is connected by bistable switches controlled at one or the other of a first or of a second output terminal, by means of current/voltage converters, said second output terminal moreover receiving an additional current i₀ /2^(n).
 3. A device according to claim 2, wherein the switch which is connected to the resistor through which the current of intensity io passes, is maintained in its position of connection to the first terminal, whilst the other switches are connected either to the first terminal or the second terminal, so as to obtain, due to current/voltage converters, voltages respectively equal to V+ΔV and ΔV-ΔV, the variation ΔV being adjustable by tipping certain of said other switches.
 4. A device according to claim 1 wherein the outputs of the digital/analog converters of the two chains are connected to an adder.
 5. A device according to any one of claims 1 to 4, wherein the two chains are controlled in parallel by a common pilot oscillator of which the frequency is equal to the product of the lowest common multiple of the low frequencies f₁ and f₂ of the two sinusoidal modulation signals and of the number N of the dots of synthesis per period of said signals and wherein, in each chain, upstream of the digital generator, a digital divider is provided which is capable of supplying to said generator the frequency Nf₁ or Nf₂ corresponding thereto.
 6. A device according to claim 5, wherein each digital divider comprises two ratios of division so that each of the chains may produce one or the other of said low frequencies f₁ or f₂, so that, when one of the chains produces the modulation signal of frequency f₁, the other chain produces simultaneously the modulation signal of frequency f₂, and vice versa.
 7. A device according to claim 6, wherein it comprises a digital phase converter with control inputs, disposed between the two chains and capable, from the passage through the 0 degree phase of the sinusoidal modulation signal produced by one of the digital generators, to initialize the other sinusoidal modulation signal with a variable delay.
 8. A device according to claim 7, wherein the phase converter is constituted by a digital counter with programmable counting value.
 9. A device according to claim 6, wherein the counter, on the one hand, counts the pulses which arrive from a third divider connected to one of said digital generators and presenting, as desired, two ratios of division equal to those of said chain dividers and, on the other hand, is controlled by a fourth divider connected to one of said chain dividers, the ratios of division of said third and fourth dividers being simultaneously equal to each other and inverse of the ratio of division of the divider of the chain from which they receive their data. 